1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit, and more particularly relates to a PLL circuit capable of improving reliability while suppressing power consumption without degrading noise characteristics.
2. Description of the Related Art
[Conventional PLL Circuit: FIG. 9]
Referring to FIG. 9, a conventional PLL circuit is described below. FIG. 9 illustrates the configuration of a conventional PLL circuit.
As illustrated in FIG. 9, the conventional PLL circuit includes a voltage controlled oscillator (VCO) 1; a PLL integrated circuit (PLL IC: phase comparator) 2; an analog filter 3; a reference oscillator 4; a direct digital synthesizer (DDS) circuit 5; and a control circuit 6.
The VCO 1 outputs a desired oscillatory frequency Fout in accordance with a control voltage output from the analog filter 3.
The PLL IC 2 receives the oscillatory frequency Fout as input, divides the frequency with a setting value for division ratio supplied from the control circuit 6 using an output frequency Fdds from the DDS circuit 5 as a reference signal (clock), and outputs the divided frequency to the analog filter 3.
The analog filter 3 smoothes the divided frequency from the PLL IC 2 and outputs the same as a control voltage to the VCO 1.
The reference oscillator 4 includes a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), an oven controlled crystal oscillator (OCXO) or the like, and outputs a reference frequency Fref to the DDS circuit 5 in accordance with a reference frequency selection signal from the control circuit 6.
The DDS circuit 5 outputs, to the PLL IC 2, an output frequency Fdds generated based on the reference frequency Fref from the reference oscillator 4 in accordance with the Fdds selection signal from the control circuit 6.
The control circuit 6 outputs the reference frequency selection signal to the reference oscillator 4, outputs the Fdds selection signal to the DDS circuit 5, and outputs the setting data for division ratio to the PLL IC 2.
[Operation of the Conventional PLL Circuit]
In the conventional PLL circuit, the control circuit 6 outputs, to the PLL IC 2 and the DDS circuit 5, data (setting data for division ratio, Fdds selection signal) serving as a preset channel (frequency) in a system including the PLL circuit used as an oscillator for setting.
The PLL IC 2 decides a division ratio and a counter value based on the setting data, and the DDS circuit 5 decides any output frequency Fdds used as a reference signal for the PLL IC 2. Thereby, the VCO output will be a preset frequency Fout.
[Related Art]
Related art includes: Japanese Patent Application Laid-Open No. H07-131343 “Frequency synthesizer” (Applicant: ICOM INC/Patent Document 1), Japanese Patent Application Laid-Open No. 2007-208367 “Synchronizing signal generating apparatus, transmitter, and control method” (Applicant: Kenwood Corp/Patent Document 2), and Japanese Patent Application Laid-Open No. 2002-141797 “Frequency synthesizer” (Applicant: Mitsubishi Electric Corp/Patent Document 3).
Patent Document 1 discloses a frequency synthesizer, in which a memory stores a set of a reference frequency switching signal and a DDS output frequency switching signal for each output frequency and when the PLL circuit is locked, an unnecessary wave component is driven away from a pass band.
Patent Document 2 discloses a synchronizing signal generating apparatus, in which a frequency division ratio N of a frequency divider (1/N), an output frequency/input frequency of a DDS, a frequency division ratio Ma of a frequency divider (1/Ma) and a number of multiple Mb of a multiplier (×Mb) are adjusted so that the transmission wave has the instructed frequency and a combination of the input frequency and the output frequency in the DDS has spurious in the output of the DDS at a prescribed level or below.
Patent Document 3 discloses a frequency synthesizer that lets the output of DDS pass through a narrow-band variable frequency filter before inputting it to a phase synchronous loop, so as to change a center frequency of the filter, thus removing spurious.